FPGA Verification Engineer

DESCRIPTION

abra is hiring an FPGA Verification Engineer to ensure the quality and correctness of the most complex FPGA components. The role involves building modern self-checking testbenches, writing verification plans, and achieving full coverage of logic implemented in VHDL/Verilog. You will work closely with FPGA developers and system engineers to ensure our products are robust and fully reliable.

Responsibilities

Define and build verification environments from scratch at both Block and Top levels.
Write SystemVerilog testbenches using advanced methodologies (UVM – strong advantage).
Perform simulations and analyze results (Directed & Random testing).
Define and track coverage metrics (Code & Functional) to ensure verification goals are met.
Work with leading simulation tools such as ModelSim, Questa, or Vivado.

REQUIREMENTS
Bachelor’s degree in Electrical, Electronics, or Computer Engineering
3–4 years of experience in FPGA/ASIC verification
Strong proficiency in SystemVerilog or Specman (e)
Experience with structured verification methodologies such as UVM, OVM, or VMM