עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
25,000-35,000 ₪
Design and verify custom digital hardware components and architectures that enable high-performance, tightly integrated computation workloads and interface custom tensor unit for advanced AI/ML applications.
Responsibilities
Design, implement, and verify RTL blocks for memory, control, and compute subsystems within custom multiphysics computation unit.
Collaborate with system software and architecture teams to define block-level specifications and ensure alignment with performance and integration goals.
Develop and maintain functional verification infrastructure to validate design correctness across simulation and hardware testbenches.
Support synthesis, timing analysis, and backend integration, working closely with physical design and CAD engineers.
Contribute to architectural exploration and hardware-software co-design efforts to shape future iterations of compute platform.
Responsibilities
Design, implement, and verify RTL blocks for memory, control, and compute subsystems within custom multiphysics computation unit.
Collaborate with system software and architecture teams to define block-level specifications and ensure alignment with performance and integration goals.
Develop and maintain functional verification infrastructure to validate design correctness across simulation and hardware testbenches.
Support synthesis, timing analysis, and backend integration, working closely with physical design and CAD engineers.
Contribute to architectural exploration and hardware-software co-design efforts to shape future iterations of compute platform.
Requirements:
Extensive experience in RTL design (Verilog/SystemVerilog) for control logic, datapaths, memory subsystems, and specialized processing units.
Strong understanding of digital architecture, including pipelining, arbitration, memory hierarchy, and system-level integration.
Proficiency in functional verification, including testbench development, assertions, coverage metrics, and debugging (UVM experience is a plus).
Familiarity with ASIC and FPGA design flows, including synthesis, timing closure, and DFT.
Comfortable working across the full hardware stack - from architectural specification and microarchitecture to physical implementation support.
Language: English at a proficient level. French is a plus.
Extensive experience in RTL design (Verilog/SystemVerilog) for control logic, datapaths, memory subsystems, and specialized processing units.
Strong understanding of digital architecture, including pipelining, arbitration, memory hierarchy, and system-level integration.
Proficiency in functional verification, including testbench development, assertions, coverage metrics, and debugging (UVM experience is a plus).
Familiarity with ASIC and FPGA design flows, including synthesis, timing closure, and DFT.
Comfortable working across the full hardware stack - from architectural specification and microarchitecture to physical implementation support.
Language: English at a proficient level. French is a plus.
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
הוד השרון
בוקר
36 חודשים
תעודה ממשלתית
סבסוד
רמת גן
