Power Integrity Engineer

A premier, market-leading global technology Unicorn engineering disruptive hardware and networking infrastructure solutions designed to exponentially scale network throughput while driving significant operational efficiencies.

Operating at the intersection of high-performance computing, advanced silicon, and network virtualization, the enterprise delivers mission-critical foundations relied upon by tier-one telecommunications carriers and hyperscale cloud data centers worldwide.

Backed by substantial late-stage venture capital funding from prominent global institutional investors, the organization combines massive international presence with a flagship local R&D center solving complex low-level engineering challenges.

Located in an accessible technology center in the Central / Sharon district, operating on a flexible hybrid work model offering 1–2 days of remote work per week.

Position Overview-

• Senior Power Integrity (PI) & Hardware Design Engineer joining an elite, core hardware engineering group reporting directly to the Hardware Team Leader.
• Taking end-to-end technical ownership over the Power Integrity (PI) domain for next-generation, high-speed Networking platforms tailored for AI infrastructures and cutting-edge Data Centers.
• Driving comprehensive PI simulation, analysis, and validation pipelines, working directly with ultra-advanced, high-performance ASICs and complex system architectures.
• Partnering closely with world-class silicon architects, board designers, and system layout experts to architect robust power delivery networks (PDN) under extreme thermal and performance conditions.
• Core Domain & Ecosystem- Power Integrity (PI), Hardware & Board Design, High-Speed Networking Platforms, AI & Hyper-scale Data Center Infrastructure, Advanced ASIC Integration, PDN Simulation, Signal Integrity (SI) Collaboration.

Requirements

• Academic Background: B.Sc. in Electrical Engineering, Electronics Engineering, or a highly related academic discipline – Mandatory
• 5+ years of proven professional experience dedicated to Power Integrity (PI), Advanced Hardware Design, or closely related low-level electrical engineering fields – Mandatory
• Deep, practical proficiency utilizing industry-standard PI simulation and modeling software tools (e.g., Ansys SIwave/HFSS, Cadence Sigrity, Keysight ADS, or equivalent) – Mandatory
• Hands-on experience with high-speed board layout design, power delivery networks (PDN) optimization, and decoupling capacitor placement strategies – Mandatory
• Proven background evaluating complex power domains for high-power components, specifically advanced ASICs, FPGAs, or SoCs – Mandatory
• Strong laboratory validation capabilities, including hands-on experience with high-frequency test equipment (oscilloscopes, VNAs, spectrum analyzers) – Advantage
• Exceptional analytical problem-solving skills with a collaborative approach to bridging complex silicon requirements with physical board design realities – Mandatory