Senior Power Integrity Engineer

Experience with high-performance networking ASICs and switch silicon.
Familiarity with 112G/224G/448G PAM4 SerDes technologies.
Experience with Ethernet systems ranging from 400G to 1.6T and above.
Understanding of package-level PI and advanced packaging technologies.
Familiarity with optical networking platforms and co-packaged optics.
Experience with thermal and mechanical effects on PDN performance.
Knowledge of EMI/EMC considerations in high-density networking systems.
Experience working with ODMs, CMs, and global manufacturing partners.
Success Metrics

Achieve PI sign-off requirements for all networking platforms.
Minimize power-related issues during bring-up and production.
Improve first-pass hardware success rate.
Enable reliable operation of next-generation high-bandwidth networking systems.
Establish scalable PI methodologies for future DriveNets hardware platform
דרישות התפקיד
B.Sc. or M.Sc. in Electrical Engineering.
5+ years of experience in Power Integrity, Hardware Design, or related disciplines.
Strong understanding of power delivery networks, decoupling methodologies, and target impedance concepts.
Hands-on experience with PI simulation tools such as:
Cadence Sigrity PowerSI / OptimizePI
Ansys SIwave
Ansys HFSS
PowerDC or equivalent
Experience designing high-layer-count PCBs for networking, telecom, server, or data-center products.
Knowledge of high-speed digital systems and interaction between Signal Integrity and Power Integrity.
Experience with multi-phase voltage regulators, power sequencing, and power management architectures.
Strong understanding of PCB materials, stackups, and manufacturing constraints.
Experience performing lab validation and correlation measurements.
Excellent problem-solving, communication, and teamwork skill