FPGA Design Engineer

About the Position

Nuvoton Israel, located in Herzliya, is a leading fabless semiconductor company developing cutting-edge ASIC solutions for the Cloud and Enterprise markets.

Our products—integrated ASIC chips with embedded software—are deployed in the tens of millions worldwide across a diverse range of computing systems.

We partner with Tier-1 PC and Server OEMs, including HP, Dell, Google, and Microsoft, to define the future of hardware security and cloud infrastructure.

At Nuvoton, we leverage FPGA technology to emulate our ASIC designs and their system environments.

This is a critical pillar of our design validation process and provides the essential early prototyping platform for firmware development.

We are looking for an experienced, self-starting FPGA Engineer to join our HW team.

In this role, you will operate independently and collaborate with multiple R&D teams to produce, debug, and utilize high-quality FPGA designs that bridge the gap between concept and silicon.

Key Responsibilities

• Own the entire FPGA development lifecycle, from design entry to timing closure.
• Develop FPGA-based emulation platforms for complex ASIC designs.
• Independent execution of synthesis, place & route, and timing constraints.
• Collaborate with Hardware and Firmware teams to debug system-level issues in the lab.
• Establish and follow orderly work procedures to ensure high-quality design standards.

Requirements:

Must-Haves:

• Education: B.Sc. in Electrical Engineering.
• Experience: 5+ years of proven experience in FPGA design.
• Languages: Deep knowledge of Verilog and/or VHDL.
• Tools: Hands-on experience with Altera (Intel) and Xilinx (AMD) flows (Design Entry, Synthesis, P&R).
• Timing: Demonstrated expertise in defining timing constraints and achieving timing closure.
• Lab Skills: Practical experience in a lab environment using standard test and debug equipment (oscilloscopes, logic analyzers).

Advantages:

• Experience with on-chip debug tools (e.g., ChipScope, Signal Tap).
• Familiarity with verification methodologies, including RTL and Gate-Level simulation tools.
• Knowledge of logic design and/or VLSI backend flows.