FPGA Verification Engineer

FPGA Verification Engineer

A leading defense company is looking for a FPGA Verification Engineer.

This role involves developing and executing advanced verification environments for FPGA components, supporting existing environments, and reporting on functional coverage.

Responsibilities:

• Build and run Random Based Verification environments using SystemVerilog and UVM.
• Write scripts in Python and TCL for testing and automation.
• Support legacy verification environments in Verilog / VHDL / SystemVerilog.
• Integrate verification environments and report Functional Coverage.
• Work with UVM Register Model and Scoreboard.

Requirements:

• B.Sc. in Electrical Engineering (mandatory).
• At least 3 years of experience in verification.
• Hands-on experience with UVM, Reuse principles, and functional coverage.
• Proven experience integrating verification environments.

Advantages:

• Knowledge of Assertion Based Verification.
• Experience with VIP integration.
• Familiarity with communication protocols: AXI, SPI, I2C, ETH, PCIe.
• Experience in VHDL / Verilog design.