VLSI Design Engineer

Who We Are?

We are a growing startup company revolutionizing the Storage Processor world, with an ingenious solution. Founded in 2017 by industry leaders. We’re the cream of the crop, with a positive disposition, an optimistic vibe, and a can-do attitude.

We’re stronger together, at home and at work. Our mind is sharp and we’re quick on our toes, we lead by sharing, and empower by advising where to look but not what to see. Honestly, we're quite knowledgeable, however, we know there’s a lot more gray matter to color with learning.

Our Extreme Data Processor (XDP) is a hardware-based storage accelerator that enables cloud and enterprise customers to offload and accelerate data-intensive workloads using just a fraction of the computational load and power. It’s truly groundbreaking, you have to see it to believe it.

Pliops does not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity or expression, national origin, age, disability, veteran status, marital status, or based on an individual's status in any group or class protected by applicable federal, state or local law. Pliops encourages applications from minorities, women, the disabled, protected veterans and all other qualified applicants.

To find out more about us, click on the link below:

Pliops Extreme Data Processor Explained

https://www.themarker.com/labels/israel-success/1.10772837

In this role, you will be:

• Responsible for definition and micro-architecture of complicated digital blocks
• Detailed documentation and RTL implementation including running EDA tools (Lint, CDC, simulation, debugging, synthesis and timing analysis)
• Work closely with verification and architecture team
• Participate in design methodology and tool automation work as needed
  
  

• B.Sc. in Electrical Engineering
• Minimum 5 years of experience in logic design from semiconductor companies
• Knowledge and experience in Verilog and/or System Verilog
• Knowledge of power management techniques for low power design
• Familiarity with Clock domain crossing, simulation, debugging, synthesis and timing analysis
• Knowledge in scripting languages such as Python or Perl – Advantage
• Very good communication skills