Senior Verification Engineer

Tel Aviv
About The Position

We are developing a next-generation compute-acceleration chip designed to power the future of LLM inference, the most compute-hungry and fastest-growing workload in AI.

As the world pours trillions of dollars into scaling data-center AI, a massive bottleneck is emerging: delivering far more inference throughput at dramatically lower power. LLM inference now dominates the operational cost of AI, and accelerating it has become one of the most critical challenges in the entire industry.

Our mission is to build a breakthrough architecture that leapfrogs today’s solutions from NVIDIA, AMD, Google TPU, AWS Trainium/Inferentia, Intel Gaudi, Cerebras, and others — enabling unprecedented efficiency, throughput, and scalability.

We operate in true startup mode: fast-paced, ambitious, and deeply technical. The project is complex and schedule-challenging across architecture, RTL, verification, and system design — and we are looking for a Senior Verification Engineer who wants to work hard, move fast, and help build something truly new.

The Senior Verification Engineer will join a high-end team responsible for verifying a high-performance controller ASIC at the core of this new computational paradigm.

Your Day to Day
Define, architect, and develop advanced verification environments and flows using SystemVerilog UVM
Build block-level, subsystem-level, and full-chip verification environments with reusable methodology
Develop coverage-driven verification strategies and automation infrastructure
Work closely with design, architecture, algorithms, and software teams to define functionality and corner cases
Drive testplan creation, functional coverage definition, and closure across multiple complex blocks
Debug intricate logic interactions, multi-clock structures, and high-speed data paths
Contribute to verification methodology, tooling, infrastructure, and continuous improvement
Participate in a fast-moving, startup-style environment where deep technical ownership and rapid iteration are essential
Requirements

Required

At least 5 years of experience in functional verification
At least 3 years of hands-on experience with UVM / SystemVerilog
BSc/MSc in Electrical Engineering, Computer Engineering, or Computer Science
Proven track record in planning, executing, tracking, and closing complex verification tasks
Strong understanding of coverage-driven verification methodologies
Excellent problem-solving and debugging skills
Experience working in Linux environments
Strong communication skills and comfort working cross-functionally
Self-motivated, detail-oriented, and capable of deep ownership
Fluent in English, both verbal and written

Advantages

Experience verifying high-speed ASICs, multi-clock systems, and complex synchronization schemes
Familiarity with high-speed interfaces such as PCIe, Aurora, Ethernet PHYs, or custom SERDES links
Experience in full-chip or SoC-level verification
Knowledge of scripting languages (Python, Perl, Tcl)
Why should you be a TriEyoneer?
Work on breakthrough AI acceleration technology that has the potential to reshape data-center compute
Join a fast-growing deep-tech environment backed by industry leaders
Be part of a highly talented, multidisciplinary team solving cutting-edge engineering problems
Modern offices in Tel Aviv with an excellent work environment
Competitive benefits package: Free gym membership, parking, holidays and birthday gifts, Cibus, generous vacation allowance, happy hours, team events, etc
General statement

TriEye is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.