Verification Engineer

Verification Engineerזיהוי דרישה: 3278מיקום גאוגרפי: מרכזחברה: ElbitSystemsעיר:Elbit Systems Ltd. is an international technology company that specializes in defense, homeland security, and commercial programs worldwideThe company operates in aerospace, land, and naval systems, C4ISR, unmanned aircraft systems, advanced electro-optics, EW suites, signal intelligence systems, data links and communications systems, radios and cyber-based systems, and munitionsElbit Systems develops new technologies for defense, homeland security, and commercial applicationsRole DescriptionWe are seeking a Verification Engineer to join our dynamic team, specializing in System Verilog and UVM methodologyYou will be responsible for designing and implementing verification plans, utilizing UVM to ensure comprehensive coverage and efficiency, Plan the verification of complex digital design by fully understanding the design specification and the implemented algorithmsYou will collaborate with cross-functional teams to identify and resolve design issues, and contribute to the continuous improvement of our verification processes, Working closely with architecture, design and algorithm teams to identify important verification scenariosYour contributions will have a direct impact on our vital defense capabilitiesKey ResponsibilitiesResponsible for the entire Verification cycle, from initial requirements gathering to achieving full coverageSteps will include developing a detailed Test Plan, creating and optimizing the UVM environment, implementing comprehensive Coverage strategies, and integrating a Scoreboard for effective verification and validationCollaborate closely with a multidisciplinary team of engineers to ensure our FPGA solutions align with the stringent requirements of our high-performance end productsAdapt to evolving project needs, demonstrating flexibility and innovation in your approachSkills and QualificationsBachelor's or Master's degree in Electrical Engineering, Computer Science, or a related fieldFour years of experience with UVM methodology and System VerilogExperience with RTL debugging from Block level to System LevelExperience with Questa Simulator - advantageVHDL/Verilog proficiency – advantageTCL/Python/bash experience – advantageLinux/NC experience – advantage