Verification Engineer

A high-profile, venture-backed US-Israeli semiconductor scale-up engineering next-generation optical communication silicon and foundational hardware accelerators for large-scale AI infrastructures and hyperscale Data Centers.

Backed by hundreds of millions of dollars in capital from premier tier-one investors and strategic tech giants, the company operates with a world-class chip design center in Israel.

The company develops programmable high-speed coherent DSP processors utilizing advanced deep-submicron process nodes (5nm), enabling ultra-high-bandwidth, power-efficient optical connectivity bridging GPUs, compute clusters, and cloud fabrics.

Combining elite silicon engineering with massive commercial market demand across global AI data centers, the company provides an exceptional environment for cutting-edge VLSI and mixed-signal verification.

Located in the Central District directly adjacent to primary train transit, operating on a hybrid model.

Role Description-

• Serving as a Mixed-Signal / Analog Verification Engineer, joining the core chip verification squad to define, architect, and execute verification strategies for complex analog and mixed-signal silicon blocks.
• Developing high-fidelity behavioral models (real-number modeling / behavioral abstractions) for complex analog and mixed-signal circuitry.
• Architecting and maintaining advanced verification testbenches utilizing SystemVerilog and UVM methodologies.
• Executing dynamic mixed-signal verification utilizing leading AMS tools and digital chip design simulation environments.
• Driving rigorous simulations across all integration tiers: from standalone IP blocks and analog clusters up to full-chip system-level validation.
• Collaborating closely across R&D with Analog Circuit Designers, Digital Architecture squads, and System Engineering teams to ensure first-pass silicon success.

Requirements-

• 2 years of professional experience in Analog Verification / Mixed-Signal Verification – Mandatory
• Proven hands-on track record in Mixed-Signal dynamic verification utilizing Digital Chip Design simulation tools – Mandatory
• Strong practical programming proficiency in Verilog and SystemVerilog – Mandatory
• Solid foundational understanding of Analog Circuit Design concepts – Mandatory
• Experience authoring verification plans, building structured testbenches, and debugging complex simulation failures – Mandatory
• Collaborative engineering approach and fluent professional communication in English (written and verbal) – Mandatory