Formal Verification Engineer- Herzliya/

SummaryPosted: Nov 21, 2023Role Number:200023014Ready for an intellectual challenge that combines Mathematics and CS theory in the context of hardware development? Keep reading. In this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence Not in the Formal domain? No worries, we offer thorough training to learn the theory and practice directly from our team expertsKey QualificationsExcellent graduates from leading universitiesAnalytical thinkingHighly motivatedDescriptionIn this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence . The position is relevant for both Herzliya/ Haifa siteEducation & ExperienceB.Sc. in Computer Science, Electrical/Computer Engineering, M.Sc/PhD MathematicsAdditional RequirementsAdditional Requirements