Formal Verification Engineer

At Ceva, we are at the forefront of DSP ASIC development, pioneering projects in AI, Vision, Wireless, Base-stations, and accelerators. We are in search of a Formal Verification Engineer to enhance our cross-business unit FV team.In this role, you will join our Formal Verification team, executing full verification cycle from architectural definition and FV strategy definition to full execution and final sign-off, utilizing advanced Formal Verification methodologies and tools.This role allows for independent work, impactful input, and substantial contributions to the VLSI department’s verification tasks.Requirements:Bachelor’s degree in Electrical Engineering from a leading university.1-2 years’ experience in Formal Verification.Proficiency in System Verilog is essential.Practical experience with Jasper is beneficial; familiarity with SV-UVM, Python, and Tcl is advantageous.A proactive, self-driven individual with problem-solving and complex analysis capabilities.Capable of delivering results in a dynamic, agile environment, both independently and organization-wide.