Formal Verification Engineer

R&DFormal Verification EngineerHaifaFull timeMobileye's EyeQ Platform Group (EPG) is seeking a motivated Formal Verification Engineer to join our team and contribute to development of hardware verification environments. This position offers an opportunity to apply formal methods to verify the correctness of various complex digital systems. This is an exciting opportunity to join a team of talented engineers, working cutting edge technologies in the field of autonomous vehicle.What will your job look like:Be the owner of formal verification environment from first draft to sign-off stageApply formal methods to verify the correctness of various complex digital systemsWork with HW architects\designers to define assumptions, rules and cover propertiesHelp define the formal verification methodology and environment to be applied by the teamExplore new Formal methods and ToolsWork with tools like Cadence JasperGold, Verisium manager, Xcelium, IndagoAnalyze verification results, identify bugs, and collaborate with engineers to resolve design issuesDevelop generic formal blocks\functions of commonly used logic, to be later used off the shelfAll you need is:BSc in electrical engineering, computer engineering, or computer sciencePassion for the field of Formal Verification3+ years of experience in Formal VerificationUnderstanding and mastering hardware description languages (HDLs) like Verilog/SystemVerilog and programming languages such as Python or C++Strong analytical and problem solving skillsAbility to work independently and in a team-oriented environmentParticipating in last semester Formal Verification course in the Technion - advantage.Mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. If you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!