Verification Engineer

May 31, 2026
Valens HQ, Hod Hasharon, Israel
R&D
Full Time
About the Role

We are looking for a talented and motivated Verification Engineer to join our cutting-edge R&D team. In this role, you will take ownership of developing and maintaining advanced simulation environments used throughout the hardware development lifecycle — from RTL block-level testing to full-chip integration and FPGA validation.

You’ll work closely with multidisciplinary teams including Design, Architecture, DSP, Software, Product, and Validation, to ensure robust and efficient verification processes across a dynamic and innovative engineering environment.

Key Responsibilities

Define and develop simulation and verification environments (testbenches and frameworks) for complex SoC designs.
Support RTL development and full-chip integration through verification planning, test writing, and debugging.
Analyze and resolve functional issues discovered during simulation or integration phases.
Drive continuous improvement in verification methodologies and flows.
Collaborate cross-functionally to align with architecture and design specifications.

Requirements

B.Sc. in Electrical Engineering from a recognized university.
Minimum of 3 years of hands-on experience in ASIC/FPGA verification
Strong knowledge in verification methodologies, simulation tools, and debugging.
Excellent communication and teamwork skills — ability to thrive in a fast-paced, collaborative environment.
Advantageous Experience:
Experience with Specman/e.
Familiarity with UVM (Universal Verification Methodology).