עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
25,000-35,000 ₪
This revolutionary mixture of cloud and semiconductor technology is being used by some of the worlds largest consumer, retail, food and pharmaceutical companies to change the way we make, distribute, sell, use and recycle products.
Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm and PepsiCo.
Responsibilities
Design and implement complex digital circuits for ultra low-power SoC.
Participate in all phases of SoC design, from specification to coding, debug and tape-out.
Perform RTL design, synthesis, and timing analysis.
Optimize designs for power, performance, and area (PPA).
Collaborate with cross-functional teams, including architecture, System, Software, Analog, verification, and physical design engineers.
Contribute to the development of design methodologies and best practices.
Debug and resolve design issues.
Support Lab bring ups, debug and other activities
Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm and PepsiCo.
Responsibilities
Design and implement complex digital circuits for ultra low-power SoC.
Participate in all phases of SoC design, from specification to coding, debug and tape-out.
Perform RTL design, synthesis, and timing analysis.
Optimize designs for power, performance, and area (PPA).
Collaborate with cross-functional teams, including architecture, System, Software, Analog, verification, and physical design engineers.
Contribute to the development of design methodologies and best practices.
Debug and resolve design issues.
Support Lab bring ups, debug and other activities
Requirements:
Bachelor's Or Master's degree in Electrical Engineering, Computer Engineering, or a related field
Minimum 5 years of experience in logic design, working in both IP and SOC environments
Proficiency in Verilog or SystemVerilog for design
Experience with industry-standard EDA tools (Synopsys VC, Cadence etc)
Knowledge in low power design techniques
Knowledge of RTL synthesis and timing analysis flows
Strong communication and teamwork abilities
Excellent problem-solving and debugging skills
Bachelor's Or Master's degree in Electrical Engineering, Computer Engineering, or a related field
Minimum 5 years of experience in logic design, working in both IP and SOC environments
Proficiency in Verilog or SystemVerilog for design
Experience with industry-standard EDA tools (Synopsys VC, Cadence etc)
Knowledge in low power design techniques
Knowledge of RTL synthesis and timing analysis flows
Strong communication and teamwork abilities
Excellent problem-solving and debugging skills
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
תל אביב - יפו
ערב
8 חודשים
