Logic Design Engineer

A premier, globally distributed Deep Tech and Semiconductor scale-up pioneering breakthrough High-Performance Computing (HPC) architectures and custom hardware accelerators for next-generation Artificial Intelligence.

Operating across multiple international R&D centers with a global workforce of several hundred engineers and a primary core engineering hub in Israel, the company designs foundational silicon architectures that fundamentally transform compute density, memory bandwidth, and power efficiency for massive AI models and hyperscale cloud datacenters.

Combining formidable financial backing and extensive scale with an elite, multidisciplinary engineering culture, the company offers direct ownership over core hardware programs at the absolute frontier of computing.

Located in the Central District directly adjacent to primary train transit, operating on a hybrid model with two days working from home.

Role Description-

• Serving as a Senior Digital Design (RTL) Engineer, leading the design, micro-architecture, and implementation of complex digital IP blocks for next-generation AI and HPC accelerator silicon.
• Holding complete technical ownership over block-level development: translating high-level architectural and system specifications into detailed micro-architecture design documents (MAS) and efficient RTL implementation.
• Driving digital implementation from Micro-Architecture to Gate-Level Netlist, continuously optimizing for performance, timing closure, area, and power efficiency (PPA).
• Executing rigorous Front-End design quality checks, including Lint analysis, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), static power analysis, and functional simulations.
• Collaborating cross-functionally across multi-disciplinary engineering squads: partnering with System Architecture to define specs, Physical Design (Backend) for synthesis and timing closure, Pre-Silicon Verification teams for testbench coverage, and Software/Firmware teams for hardware-software interface validation.

Requirements-

• B.Sc. in Electrical / Electronics Engineering, Computer Engineering, Computer Science, or equivalent – Mandatory
• At least 5 years of proven professional experience in digital RTL design (SystemVerilog / Verilog) for complex ASIC / SoC blocks – Mandatory
• Proven track record translating high-level system and architectural requirements into comprehensive Micro-Architectural Specifications (MAS) and robust RTL code – Mandatory
• Deep, proven hands-on experience in Front-End sign-off tooling and static checks: CDC, Lint, Power analysis, and Simulation tools – Mandatory
• Solid technical understanding of timing closure principles, static timing analysis (STA), synthesis constraints, and power-aware design methodologies – Mandatory
• Strong multidisciplinary interface capabilities (Architecture, Physical Design, Verification, and SW/FW) and fluent professional communication in English (written and verbal) – Mandatory