עדיין מחפשים עבודה במנועי חיפוש? הגיע הזמן להשתדרג!
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
מלאה
25,000-40,000 ₪
Join our team in a pivotal role where you'll own the entire IP-level netlist generation and timing convergence journey from synthesis to sign-off.
You'll drive synthesis, UPF power intent, scan insertion, and external IP integration while architecting timing constraints for both standard and complex custom designs that ensure sign-off quality from day one.
Working at the intersection of multiple disciplines, you'll partner closely with RTL designers to deeply understand design intent and clock architecture, collaborate with CAD teams to shape and optimize cutting-edge flows, and team with Physical Design engineers to achieve flawless timing sign-off.
We're seeking an innovative thinker who brings fresh perspectives to timing analysis methodologies and proactively identifies and resolves timing challenges to eliminate pessimism and accelerate convergence, ultimately making their mark on next-generation chip design.
You'll drive synthesis, UPF power intent, scan insertion, and external IP integration while architecting timing constraints for both standard and complex custom designs that ensure sign-off quality from day one.
Working at the intersection of multiple disciplines, you'll partner closely with RTL designers to deeply understand design intent and clock architecture, collaborate with CAD teams to shape and optimize cutting-edge flows, and team with Physical Design engineers to achieve flawless timing sign-off.
We're seeking an innovative thinker who brings fresh perspectives to timing analysis methodologies and proactively identifies and resolves timing challenges to eliminate pessimism and accelerate convergence, ultimately making their mark on next-generation chip design.
Requirements:
Qualifications
Bsc/Msc in Electrical Engineering
5+ years of experience in the field
At least 2+ years of experience in writing ASIC timing constraints and achieving timing closure
Expertise in STA tools (Primetime) and flow generation
Knowledge of the ASIC design timing closure flow and methodology
Preferred Qualifications
Understanding of timing corners/modes
Familiarity with process variations and signal integrity-related issues
Hands-on experience in generating and managing timing/SDC constraints, proficient in scripting languages (Tcl and Perl)
Knowledge of synthesis, DFT, and backend-related methodologies and tools
Strong communication skills are required, as you will interact with various groups
Qualifications
Bsc/Msc in Electrical Engineering
5+ years of experience in the field
At least 2+ years of experience in writing ASIC timing constraints and achieving timing closure
Expertise in STA tools (Primetime) and flow generation
Knowledge of the ASIC design timing closure flow and methodology
Preferred Qualifications
Understanding of timing corners/modes
Familiarity with process variations and signal integrity-related issues
Hands-on experience in generating and managing timing/SDC constraints, proficient in scripting languages (Tcl and Perl)
Knowledge of synthesis, DFT, and backend-related methodologies and tools
Strong communication skills are required, as you will interact with various groups
This position is open to all candidates.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
תל אביב - יפו
