Senior Static Timing Analysis (STA) Engineer (IL)

Description

Job Summary

We are seeking a highly skilled Senior Static Timing Analysis (STA) Engineer to join our ASIC implementation team. The ideal candidate will have extensive experience in timing analysis, timing closure, and signoff for complex SoC designs at advanced technology nodes. The engineer will work closely with RTL, Physical Design, DFT, and CAD teams to ensure successful timing convergence and tape-out.

Key Responsibilities

• Own full-chip and block-level timing closure from synthesis through signoff.
• Perform static timing analysis across multiple operating modes and PVT corners.
• Develop, review, and maintain timing constraints (SDC).
• Analyze and resolve setup, hold, recovery, removal, clock gating, pulse width, and timing exception violations.
• Perform SI-aware timing analysis and crosstalk delay/noise debugging.
• Collaborate with Physical Design teams to optimize placement, CTS, routing, and ECO implementation for timing closure.
• Generate and validate timing ECOs while ensuring minimal impact on power, area, and functionality.
• Validate timing exceptions including false paths, multicycle paths, asynchronous paths, and generated clocks.
• Perform timing signoff using industry-standard EDA tools.
• Support timing correlation between implementation and signoff environments.
• Develop automation scripts to improve timing analysis and reporting.
• Participate in design reviews and provide technical guidance on timing-related issues.
• Mentor junior engineers and contribute to methodology improvements.
  
  

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 5 years of experience in ASIC Static Timing Analysis or Physical Design.
• Strong understanding of:
• Static Timing Analysis fundamentals
• Timing constraints (SDC)
• MCMM timing analysis
• Clock tree architecture and clock propagation
• Signal Integrity (SI)
• OCV, AOCV, POCV, and SOCV methodologies
• CRPR and advanced variation modeling
• Liberty (.lib), SPEF, SDF, and Verilog formats
• Experience with advanced technology nodes (16nm, 7nm, 5nm, 3nm, or similar).
• Strong debugging and root-cause analysis skills.
  
  

• Proficiency with STA and implementation tools such as:
• Synopsys PrimeTime
• Synopsys Fusion
• Cadence Innovus
• Cadence Tempus
• Synopsys StarRC
• Experience with Linux/Unix environments.
• Strong scripting skills in Tcl and Shell; familiarity with Perl or Python is preferred.
• Experience with version control systems such as Git.
  
  

• Experience with hierarchical and full-chip timing signoff.
• Experience with timing signoff automation and methodology development.
• Understanding of synthesis, place-and-route, and physical implementation flows.
  
  

• Strong analytical and problem-solving abilities.
• Excellent communication and collaboration skills.
• Ability to work independently and manage multiple priorities.
• Attention to detail and commitment to design quality.
• Experience mentoring junior engineers and contributing to technical leadership.
  
  

• Ownership of timing closure for complex ASIC or SoC designs.
• Ability to drive timing signoff independently while collaborating effectively across cross-functional teams.
• Expertise in advanced timing methodologies, SI-aware analysis, MCMM signoff, and ECO execution.
• A proactive mindset focused on continuous improvement, automation, and delivering successful tape-outs.