Security Formal Verification Lead

We are looking for a Formal Verification (FV) expert to lead the formal verification of the security features in our chips. This role is in the FV team, but you will work with key stakeholders across chips in both the security architecture and RTL designs, located in different geographies. You will define the required methodology ensuring that security features are following the specification of our next generation chip designs. You will also prioritize execution of which features need to be verified when and how. You will define the FV scope and work with different FV tools to decide the best solutions. You are a hands-on FV engineer. As needed, you will also partition work for other FV engineers as needed. You will employ advanced formal techniques to obtain sufficiently bounded proofs while working with architects, designers, and pre- & post-silicon verification teams to accomplish your tasks.

What you will be doing:

Define formal verification flows and requirements for security features.

Identify key security behaviors for verification to write clear testplans for complex designs.

Implement testplans using the latest formal techniques, including the development of environment assumptions, assertions, and cover properties.

Drive verification of hardware features that improve security of our chips.

Use black-boxing, proof decompositions and abstractions to overcome complexity challenges and obtain full proofs, or bounded proofs with sufficient coverage.

Drive FV tools to realize their best performance.

Debug RTL to identify causes of failure scenarios.

Contribute to the flow and script development to improve team efficiency.

Articulate the security FV coverage to the design, simulation and architecture teams.