Digital Verification engineer

Design and develop verification environment for state-of-the-art Flash solution IPs, working closely with Design and Algorithm engineers.
Leading the top-level IP verification effort from planning to delivery.
Plan the verification of complex digital design IP's by fully understanding the design specification and the implemented algorithms.
Working closely with architecture, design and algorithm teams to identify important verification scenarios.
Responsible for the full life cycle of verification, from verification planning to tests execution through IP environment building using system Verilog and UVM.
Define and establish new verification methodologies in the group.
We offer unique opportunity to define IPs verification from early stages of architecture definition and all the way to Tapeout.