Senior VLSI Verification Engineer (Ra'anana)

A fast‑growing semiconductor startup is looking for a talented Senior VLSI Verification Engineer to take full ownership of block‑level and subsystem‑level verification.
If you love building verification environments from scratch, thrive in lean teams, and want real impact - this one’s for you!

What you’ll do:
• Own the full verification lifecycle
• Build advanced UVM/SystemVerilog environments
• Drive SVA‑based verification and deep debug
• Develop constrained‑random & directed tests
• Automate flows using Python + Linux
• Collaborate closely with RTL designers & architects
דרישות התפקיד:
• 4–8 years in ASIC/SoC verification
• Strong UVM, SVA, OOP background
• Python automation skills
• Passion for AI‑assisted engineering
• BSc/MSc in EE/CE

Big plus:
• SoC‑level verification experience
• Familiarity with embedded CPUs (RISC‑V / ARM) & AXI/AHB/APB