Formal Verification Graduate Engineer - Temporary position (1 year)

About Ceva:Ceva is the leader in innovative silicon and software IP solutions that enable smart edge products to connect, sense, and infer data more reliably and efficiently. We help the world’s leading semiconductor companies and original equipment manufacturers turn great ideas into extraordinary products. We create and license technology that powers the newest generation of smart edge devices, and provide innovative silicon and software IP solutions for artificial intelligence, computer vision, audio processing, sensor fusion, 5G and satellite communication, and wireless connectivity.About the role:In this role, you will join our Formal Verification team, executing full verification cycle from architectural definition and FV strategy definition to full execution and final sign-off, utilizing advanced Formal Verification methodologies and tools.This role allows for independent work, impactful input, and substantial contributions to the VLSI department’s verification tasksResponsibilities:Develop Formal Test benches and Properties - Write and maintain System Verilog Assertions to formally verify RTL designs using industry-standard formal tools.Collaborating with Design and Verification TeamsContribute to Verification Planning and CoverageDefine formal verification plans, track progress, and contribute to achieving verification completeness.Requirements:Bachelor’s degree in electrical engineering.Proficiency in System Verilog is essential.A proactive, self-driven individual with problem-solving and complex analysis capabilities.Capable of delivering results in a dynamic, agile environment, both independently and organization-wideAdvantages:Practical experience with Jasper is beneficial; familiarity with SV-UVM, Python, and Tcl is advantageous.Experience in Formal Verification or Dynamic VerificationPlease add Grades Sheet