Staff Formal Verification Engineer

Staff Formal Verification Engineer

Ready to take Formal Verification into the world of AI/ML?

We’re looking for an experienced Staff Formal Verification Engineer to join a highly skilled hardware team working on complex, next-generation technology.

You’ll take ownership of Formal Verification across complex IP blocks, build and evolve verification environments and methodologies, and work hands-on with Cadence JasperGold. The role involves close collaboration with global Design, Verification, and Architecture teams and offers significant technical ownership and influence.

What we’re looking for:

• B.Sc. in Electrical Engineering, Computer Engineering, Computer Science, Mathematics,s or a related field
• 7+ years of hands-on Formal Verification experience
• Strong hands-on experience with Cadence JasperGold
• Experience with Formal methodologies such as property checking, connectivity, equivalence checking, X-propagation, coverage,ge and bug hunting
• Strong system-level thinking and debugging skills
• Experience with SystemVerilog / Verilog – an advantage
• Background in Logic Design or Architecture – a strong advantage
• GPU / processor experience – an advantage

📍 Ra’anana | Hybrid – 2 days in the office, 3 days from home

If you’re passionate about deep hardware challenges and want to work at the intersection of Formal Verification, AI/ML,/ML and advanced silicon design, we’d love to hear from you.