Formal verification engineer 243390

Join a leading semiconductor company developing advanced communication and connectivity solutions. We are looking for a talented Formal Verification Engineer to take part in complex VLSI projects and contribute to the development of cutting-edge chip technologies.

Responsibilities

• Execute the full Formal Verification cycle from architecture review and verification planning through execution and final sign-off

• Develop and maintain SystemVerilog Assertions for RTL verification using industry-leading Formal Verification tools

• Define Formal Verification methodologies and strategies for complex designs

• Collaborate closely with Design and Verification teams to ensure comprehensive coverage and verification quality

• Create and maintain formal testbenches and verification environments

• Track verification progress and drive closure of coverage and design quality goals

• Contribute to continuous improvement of verification methodologies and best practices

Requirements

• B.Sc. in Electrical Engineering from a leading university

• Strong proficiency in SystemVerilog

• Strong analytical and problem-solving skills

• Self-motivated and proactive approach with the ability to work independently

• Ability to thrive in a dynamic and fast-paced environment

• Excellent communication and teamwork skills

Advantages

• Experience with Formal Verification or Dynamic Verification

• Hands-on experience with Jasper

• Familiarity with SV-UVM

• Experience with Python and Tcl

Why Join Us

• Work on advanced VLSI and semiconductor technologies

• Be part of an innovative and highly skilled engineering team

• Influence critical verification activities on complex products

• Opportunity for professional growth and exposure to cutting-edge technologies

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