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מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
Company:
Qualcomm Israel Ltd.
Job Area:
Engineering Group, Engineering Group > Modem Technologies
General Summary:
ASIC Design Verification Engineer
General Summary
As a Senior RTL Verification Engineer, you will lead the verification of complex subsystems and architectural features within a next-generation, high-performance RISC‑V Application Processor. You will work closely with architecture, design, modeling, software, validation, and implementation teams to ensure first-pass silicon success while meeting aggressive performance, power, and area (PPA) targets.
In this role, you will drive verification strategy, methodology, and execution from specification through tape-out, providing technical leadership in the definition of scalable verification environments, coverage closure plans, and debug methodologies. You will be expected to independently own large verification domains, influence design and architecture decisions, and mentor junior engineers.
The ideal candidate has extensive experience in CPU or SoC verification, with strong expertise in one or more of the following areas: RISC‑V architecture, CPU microarchitecture, MMU, memory hierarchy, cache coherence, interconnects, and micro-controller verification.
Responsibilities
- Lead verification efforts for complex CPU and SoC subsystems from architecture definition through tape-out.
- Define comprehensive verification strategies, test plans, coverage models, and closure criteria.
- Architect, develop, and maintain advanced UVM-based verification environments and reusable verification components.
- Drive verification execution, including stimulus development, functional coverage closure, assertions, regressions, and debug.
- Collaborate closely with architecture and design teams to review specifications, identify ambiguities, and ensure verifiability.
- Develop constrained-random, directed, and scenario-based tests to validate functional correctness and corner cases.
- Drive root-cause analysis and resolution of complex design and verification issues.
- Define and implement verification methodologies that improve scalability, quality, and productivity across the project.
- Work with software, modeling, performance, and validation teams to develop system-level verification solutions.
- Analyze verification metrics and risks, proactively driving closure plans to achieve project milestones.
- Mentor junior verification engineers and contribute to the technical growth of the team.
- Contribute to DV methodology discussions and influence verification best practices across the organization.
- CPU microarchitecture
- RISC‑V architecture
- MMU and virtual memory systems
- Cache and memory subsystems
- Coherency protocols
- Interconnect and SoC architecture
- Strong expertise in SystemVerilog and UVM.
- Experience developing scalable constrained-random verification environments.
- Experience with assertions and assertion-based verification (SVA).
- Experience with Verilog and RTL debugging.
- Strong programming skills in C/C++ and/or DPI-C.
- Experience with functional coverage planning, implementation, and closure.
- Experience debugging complex hardware and verification issues independently.
- Strong communication and collaboration skills with cross-functional engineering teams.
- Ability to communicate complex technical concepts clearly in fluent English.
- Experience verifying high-performance CPU cores or application processors.
- Knowledge of RISC‑V privileged architecture, MMU, paging, interrupts, and exceptions.
- Experience with formal verification methodologies and tools.
- Experience with performance verification and architectural validation.
- Experience with emulation or FPGA-based verification platforms.
- Experience mentoring engineers and leading technical initiatives.
- Familiarity with scripting languages such as Python, Perl, or Tcl.
- Track record of driving verification methodology improvements across multiple projects.
- Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Electrical Engineering, Systems Engineering, or related work experience.
Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 1+ year of Software Engineering, Hardware Engineering, Electrical Engineering, Systems Engineering, or related work experience.
OR
PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field.
- References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications.
If you would like more information about this role, please contact Qualcomm Careers.
במקום לעבור לבד על אלפי מודעות, Jobify מנתחת את קורות החיים שלך ומציגה לך רק משרות שבאמת מתאימות לך.
מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.
שאלות ותשובות עבור משרת ASIC Design Verification Engineer – Hod HaSharon
כמהנדס אימות תכנון ASIC בכיר ב-Qualcomm, תהיה אחראי על הובלת אימות תת-מערכות מורכבות ותכונות ארכיטקטוניות במעבד יישומים מתקדם מסוג RISC-V. תפקידך יכלול הגדרת אסטרטגיות אימות מקיפות, תוכניות בדיקה, מודלי כיסוי וקריטריוני סגירה, וכן פיתוח ותחזוקה של סביבות אימות מבוססות UVM.
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