Verification Engineer

A highly successful, global semiconductor startup that designs next-generation, high-speed connectivity chips tailored specifically for hyperscale data centers.

Operating as an elite engineering powerhouse, the company provides a collaborative environment where hardware specialists solve complex verification and design challenges on cutting-edge silicon architectures.

The company's R&D headquarters is located in Ramat Gan (exceptionally accessible, situated directly on a primary train line) and operates on a hybrid model allowing for two days of remote work per week.

Position Overview-

• Senior VLSI Verification Engineer stepping into a high-impact technical leadership role to spearhead complex RTL design verification environments.
• Designing and implementing robust block-level and system-level digital design verification environments from scratch.
• Architecting advanced, scalable verification setups using SystemVerilog and UVM methodologies.
• Identifying, defining, and coding comprehensive coverage metrics to target complex hardware corner-cases, driving designs toward absolute closure.
• Bridging verification with core design aspects, collaborating closely with RTL architects to debug complex simulation anomalies.

Requirements-

• B.Sc. in Electrical Engineering, Electronics Engineering, or an equivalent quantitative discipline (Mandatory).
• 10+ years of proven professional experience as a VLSI Verification Engineer (Mandatory).
• Proven track record of executing at least 2 full life-cycle block or system-level verification cycles from concept to tape-out (Mandatory).
• Deep, production-grade mastery of advanced verification methodologies, specifically UVM or eRM (Mandatory).
• Rich hands-on experience verifying high-speed data paths and networking protocols, such as Ethernet or equivalent architectures (Mandatory).
• Comprehensive understanding of the complete end-to-end VLSI verification flow, tools, and simulation platforms.