Senior STA Engineer, Sub-Chip

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

At NVIDIA Networking, we are driven by innovation and excellence. Our team in Israel is looking for a dedicated Chiplet STA owner to join us in defining the next era of AI's networking. This is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. If you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!

What You'll Be Doing

• Perform advanced Static Timing Analysis (STA) for HSIO at chiplet and FC level.
• Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
• Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.
• Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.
  
  

• B.SC./ M.SC. in Electrical Engineering.
• At least 4+ years of hands-on STA experience.
• Experience in Prime Time and signoff methodologies.
• Excellent leadership capabilities.
  
  

• Knowledge in physical design flows and methodologies (Synthesis, PNR, DFT designs).
• Trong background of Prime time tool.
• Great teammate.