Verification Engineer

Hailo is a leading high-tech company, developing top-performing AI processors for edge devices in various industries. We combine an extensive understanding of the way neural networks operate, with our team’s expertise in SW and HW architecture, to develop products that transform the way we use machines to perceive and analyze the world around us.

Our company is led by a group of experts from a wide range of disciplines, combining experience from elite intelligence units as well as leading tech companies in Israel and abroad, with a track record of executing complex projects from the ground up. As an AI chip company, we believe that AI can help us create a better, safer, more productive, and more convenient world. For this to happen, AI needs to be available at scale and on the edge.

To this end, our team of hardware and software leaders is developing top-performing AI processors, dedicated to AI tasks on edge devices in a wide variety of applications and industries including smart cities, automotive, manufacturing, agriculture, retail, and many more. With hundreds of customer programs around the world, and a wide ecosystem of software and hardware partners, Hailo is leading the edge AI revolution.

About The Position

Hailo is looking to hire a talented Verification Engineer to join our VLSI group in Tel Aviv.

You will work alongside other talented engineers to develop our cutting-edge AI chips. If you are motivated and skilled in VLSI and excited about AI, we want to meet you!

Responsibilities:

• Collaborate with architecture and design teams to define and implement comprehensive testcases for NN processor and SoC blocks and flows.
• Maintain, enhance, and scale the UVM‑based verification environment to support efficient and robust verification.
• Own end‑to‑end verification of system flows to ensure the design is fully functional, correct, and meets performance expectations.
• Drive root‑cause analysis and debug across RTL, testbench, and system layers to ensure high‑quality design closure.
• Define, track, and close functional and performance coverage to guarantee verification completeness.
• Continuously improve verification methodologies, automation, and workflows to increase productivity and coverage efficiency.
  
  

• B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, or a related field from a leading university.
• 3+ years of hands‑on experience in ASIC design or verification.
• Strong knowledge of SystemVerilog and the UVM verification methodology.
• Experience with SoC‑level verification is an advantage.
• Excellent problem‑solving abilities and strong communication skills.
• Proficient in written and spoken English and comfortable collaborating with a global team.