STA Engineer

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Role Overview

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Tech Lead STA Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the sign-off methodology for chips that power the world's most advanced AI clusters.

As a Tech Lead STA Engineer, you will hold the keys to silicon success. You won't just run tools—you will establish the rigorous timing criteria and methodologies that ensure our high-performance connectivity solutions meet the aggressive timing targets required for next-generation data centers. You will act as the central nervous system of the design process, bridging the gap between Architecture, Design, DFT, and Physical Design teams to drive timing closure on cutting-edge semiconductor solutions. If you thrive on solving complex challenges in deep-submicron processes and want to shape the timing methodology for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

• STA Methodology & Sign-off Ownership
• Take full ownership of the STA flow and sign-off methodologies, establishing rigorous criteria for success in demanding data center environments
• Develop, optimize, and manage complex SDC constraints from the ground up, ensuring robustness across multi-scenario environments
• Drive advanced margining methodologies including OCV, AOCV, and POCV from synthesis through final sign-off
• Timing Closure & Cross-Functional Leadership
• Lead timing reviews and collaborate with block owners to navigate the path to sign-off convergence
• Tackle challenges of cross-chip clock distribution networks and sophisticated margining techniques
• Ensure robust silicon performance across all process corners and operating conditions
• Methodology Innovation & Automation
• Participate in design methodology improvements and tool automation initiatives
• Leverage both industry-standard EDA tools and in-house automation to make sign-off processes faster and smarter
• Bridge the gap between Architecture, Design, DFT, and Backend teams through technical leadership
  

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical field
• 5+ years of hands-on experience in Static Timing Analysis (STA) at semiconductor companies
• Deep expertise in multi-scenario STA, timing/SDC constraint development and verification
• Experience working on advanced process technologies (7nm and below)
• Solid understanding of advanced margining methodologies including OCV, AOCV, and POCV
• Strong knowledge of physical design flows (P&R, Physical Verification) and their intersection with timing closure
• Full-chip perspective managing both complex macro-level designs and top-level integration
  
  

• Master's degree in Electrical Engineering, Computer Engineering, or related field
• Experience developing and validating constraints using industry-standard tools like Timing Constraints Manager (Synopsys) or TimeVision (Ausdia)
• Proven track record managing both macro-level and full-chip timing integration
• Strong background in scripting and automation (Python, TCL, Perl) to enhance timing closure efficiency
• Experience with high-speed interface designs or data center connectivity protocols