Senior Formal Verification Engineer

Samsung Israel R&D Center is looking for a Senior Formal Verification Engineer to join our team

Join the cutting-edge team at Samsung R&D Center as we embark on shaping the future of technology today. Beyond merely envisioning the horizon, we are actively pushing boundaries in various key areas of innovation. Samsung is committed to pioneering continuous advancements, delivering value to society, and fostering an environment where our employees can fully unleash their talents, creativity, and passion. Join us in building the tomorrow we envision,

The Group

An innovative team which develops cutting-edge AI technologies is looking for an experienced and enthusiastic Formal Verification engineer to establish the formal verification technology and ramp it up in the group, by developing and enhancing Formal Verification methodologies and infrastructures, and take ownership of the verification of our IP, as well as block level and integration. We are looking for people with a broad set of technical skills, who are ready to tackle some of technology’s greatest challenges, who have the ability to think outside the box and develop technologies that will define our future.

What will you do?

• Ramp up Formal Verification domain in our group, and shape the Formal strategy
• Build from scratch and fully own the end-to-end formal verification lifecycle, from verification planning, methodology definition to execution and deployment of new formal flows.
• Design, build, and maintain formal verification methodology for complex and innovative hardware designs.
• Drive the definition and implementation of scalable formal flows that grow with increasing design and project complexity.
• Collaborate closely with Architecture and Design teams to ensure correct intent, robust specifications, and efficient verification strategies.
• Act as a technical leader, influencing best practices and mentoring others in formal verification methodologies.
• Evaluate & deploy formal tools, flows, and methodologies to improve formal verification

convergence.

Requirements:

• BSc or MSc in Electrical Engineering or Computer Science.
• 5+ years of hands-on experience in formal verification.
• Strong knowledge of formal verification methodologies and convergence strategies
• Proficiency in Verilog/System Verilog.
• Comfortable working in Unix/Linux environments.
• Proven experience developing formal verification environments from scratch.
• Excellent communication, analytical, debugging and problem-solving skills.
• A creative mindset—able to think outside the box and find elegant solutions to complex verification challenges.
• Scripting skills in Python.

Advantages

• Experience in the AI hardware acceleration domain.
• Solid experience with Jasper formal verification tools.