STA engineer

Summary

We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams.

Description

You will be responsible for:nDevelop/support automated block and full chip level signoff flowsnFull Chip Timing/Noise convergence and full signoff for high quality TOnEnable hierarchical Timing flowsnPower optimizationsnGenerate block level budget and context for correlation with Full ChipnDrive custom IP integration and custom timing checks flowsnClose work with Design, DFT, architecture and Power team

Minimum Qualifications

4+ years experience in Static Timing analysisnExtensive experience with one of the commercial STA toolsnFamiliarity with hierarchical design approach, top-down design, timing and physical convergencenExperience with backend STA closure and SignoffnDeep understanding of designs' constraints developmentnGood understanding of AC timing from specs to implementationnGood understanding of DFT modes and their constraintsnGood communication skills and team playernQuick learning of flows and methods

Preferred Qualifications

Advantage - Understanding noise and signal integrity effectsnAdvantage - Timing margins fundamental from synthesis to signoffnAdvantage - Experience with scripting