Verification Engineer

Who We Are?

We’re building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems. If you’re driven by solving problems, some don’t yet have names, this is where you want to be.

The role Includes:

Develop ASIC verification environment for full chip, sub-cluster and unit levels. Responsibility for generation and execution of verification plan for challenging digital blocks/chip Development of System Verilog, UVM based protocol/traffic generators, monitors, checkers and coverage, Learn and work with great teammates

Requirements:

• B.Sc. in Electrical Engineering from Well-known leading academic institute
• Minimum of 2 years of experience in verification from semiconductor companies
• Demonstrated experience in building a complicated verification environment
• Knowledge and experience in standard verification methodologies such as UVM/OVM- an advantage
• Knowledge in Formal verification and Emulation- an advantage
• Knowledge in scripting languages such as Python or Perl- an advantage
• Very good communication skills