VLSI Engineer

An early-stage, well-funded Israeli semiconductor startup pioneering next-generation power electronics, analog & mixed-signal architectures, and power delivery technologies.

Founded by seasoned chip industry leaders with extensive design pedigrees, the company successfully secured a substantial Seed financing round to drive forward advanced voltage conversion and power management platforms for high-performance silicon systems.

Operating with a world-class, intimate founding engineering squad, the organization offers foundational technical ownership, direct architectural impact, and rapid execution within a collaborative startup environment.

The development center is located in the Sharon area, operating on a hybrid model.

Role Description-

• Serving as a Senior ASIC / SoC Verification Engineer, taking end-to-end ownership of architecting, building from scratch (0-to-1), and maintaining complete Verification Environments in SystemVerilog and UVM.
• Defining comprehensive verification test plans, stimulus generation strategies, and driving both Functional Coverage and Code Coverage closure.
• Developing robust SystemVerilog Assertions (SVA) and checkers across block, subsystem, and chip-level domains.
• Collaborating closely with RTL, Analog/Mixed-Signal, and System Design teams to perform complex root-cause failure analysis and debugging.
• Developing automated regression infrastructures, log parsing pipelines, and simulation flows using Python within Linux environments.
• Actively exploring and integrating modern AI-assisted engineering tools to accelerate testbench generation, coverage analysis, and debugging productivity.

Requirements-

• B.Sc. / M.Sc. in Electrical Engineering, Computer Engineering, or an equivalent technical field – Mandatory
• 4 to 8 years of proven hands-on experience in ASIC / SoC Design Verification – Mandatory
• Deep, practical mastery of SystemVerilog and UVM methodologies, including advanced Object-Oriented Programming (OOP) concepts – Mandatory
• Proven experience writing and applying SystemVerilog Assertions (SVA) for protocol and behavior checking – Mandatory
• Strong programming and scripting capabilities in Python for test automation, regression flows, and data parsing – Mandatory
• Solid working proficiency within Linux-based EDA simulation environments – Mandatory
• Demonstrated interest and proactive approach to adopting modern AI tools to optimize verification productivity and workflow automation – Mandatory
• Strong root-cause debugging skills, cross-functional collaboration mindset, and high self-direction – Mandatory