Formal Verification Engineer

Company Description

Veriest is an ASIC/FPGA international design house providing full-flow services, including Software, Design & Verification, and Physical Design engineering services. Founded in 2007 in Tel Aviv, Israel by a group of VLSI experts, Veriest serves leading companies in the semiconductor fabless and electronic systems industries. The company has three design centers in Israel, Serbia, and Hungary. Veriest is committed to delivering complete quality solutions suited to various phases of a product's life cycle.

This is a full-time on-site role for a Formal Verification Engineer in the Jerusalem District, Israel. The Formal Verification Engineer will be responsible for developing and implementing formal verification environments, writing and applying verification plans, and conducting formal property verification. Additional tasks include analyzing coverage results, debugging, working with design engineers to resolve issues, and reporting outcomes to ensure the accuracy and efficiency of the designs.

• Experience with developing and implementing formal verification environments and writing verification plans
• Proficiency in formal property verification and debugging skills
• Strong analytical skills and experience with coverage results analysis
• Ability to work closely with design engineers to identify and resolve issues
• Excellent written and verbal communication skills
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
• Experience in the semiconductor industry is a plus