Design Verification Engineer

🚀 We’re Hiring: Verification Engineer – Programmable Devices (FPGA)

A leading defense company is looking for a talented Verification Engineer to join our FPGA team. This is your opportunity to take part in cutting-edge projects and work with advanced verification methodologies.

What you’ll do:

• Build and run Random-Based Verification environments using SystemVerilog UVM – from test plan definition to functional coverage.
• Support existing verification environments (Verilog / VHDL / SystemVerilog).
• Write automation scripts in TCL and Python.
• Perform environment integration and implement advanced coverage and scoreboarding techniques.

What you bring:

• B.Sc. in Electrical / Electronics Engineering – must.
• 3+ years of hands-on experience in Verification.
• Proven experience in building UVM-based environments, applying Reuse principles.
• Strong knowledge in functional coverage, UVM Register Model, and UVM Scoreboard.

Nice to have (big advantage):

• Experience with Assertion Based Verification (ABV).
• Hands-on with VIPs and protocol integration.
• Familiarity with communication protocols such as AXI, SPI, I2C, Ethernet, PCIe.
• Background in design processes using VHDL / Verilog.

✨ If you’re passionate about FPGA, verification, and innovative defense technologies – we’d love to hear from you!

📩 Send your CV - [email protected] or via Easy Apply