Senior CDC Engineer, Chip Design

NVIDIA networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. We make outstanding artificial intelligence happen and accelerate Open-AI’s Chat-GPT, for example. We believe in our people and products and seek excellent people to join us!

We are looking for a CDC Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.

What You Will Be Doing

• You will play a major role analyzing the design and driving fixes as well as developing, maintaining, and improving our Lint, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) constraints and methodology for our SOCs across block level, cluster level, and/or full chip level.
• Responsibility for analyzing and optimizing the CDC and RDC sign-offs.
• Develop and maintain key CDC/RDC checks and associated sign-offs for SOCs.
• Help in driving frontend and backend assertions needed to support CDC/RDC constraints and assumptions.
  
  

• B.Sc. in Electrical Engineering from a known university.
• Excellent grades.
• 5+ years of experience in ASIC design/uarch/arch/performance.
• At least 4 years of hands on experience in writing Verilog/VHDL.
• Strong analytic capabilities, and passion for solving logical issues.
• Strong debug skills.
• Experience in Python, Tcl and Make for automation and scripting tasks.
• Ability to drive complex activities involving many interfaces and teams.
• Good communication skills.
  
  

• Experience in RTL Design, Synthesis and Timing and as an HW-architect.
• Experience with tools like Synopsys PrimeTime, Spyglass, VC-Static, or Meridian.
• Knowledge in switching fabrics with strict performance requirements. (Networking, SOC connectivity, etc).
• Familiar with working on large high-end ASICs.
• Experience in performance improvements in ASICExpertise in Static Timing Analysis (STA), Clock-Domain Crossing (CDC), and Reset Domain Crossing (RDC) solutions.