STA Backend Engineer

Who We Are?

We are a growing startup company revolutionizing the Storage Processor world, with an ingenious solution. Founded in 2017 by industry leaders. We’re the cream of the crop, with a positive disposition, an optimistic vibe, and a can-do attitude.

We’re stronger together, at home and at work. Our mind is sharp and we’re quick on our toes, we lead by sharing, and empower by advising where to look but not what to see. Honestly, we're quite knowledgeable, however, we know there’s a lot more gray matter to color with learning.

Our Extreme Data Processor (XDP) is a hardware-based storage accelerator that enables cloud and enterprise customers to offload and accelerate data-intensive workloads using just a fraction of the computational load and power. It’s truly groundbreaking, you have to see it to believe it.

Pliops does not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity or expression, national origin, age, disability, veteran status, marital status, or based on an individual's status in any group or class protected by applicable federal, state or local law. Pliops encourages applications from minorities, women, the disabled, protected veterans and all other qualified applicants.

To find out more about us, click on the link below:

Pliops Extreme Data Processor Explained

About The Position

The STA Backend Engineer position includes:

• Working closely with architecture, design and DFT teams to make sure timing closure ensures product success
• Being part of the Backend team developing highly optimized power, performance and area ASIC product from RTL to GDS
• Being responsible for the STA flow and signoff methodology
• Tracking project timeline, status and execution quality to meet project milestones
• Participating in design methodology, reviews and tool automation work as needed
• Ownership on blocks in RTL2GDS workflow - optional
  
  

• B.Sc. Degree in Electrical Engineering
• 5+ years of experience as STA/ Backend engineer from a leading semiconductor company at advanced process technology
• Hands-on experience in both Macro level and full-chip STA
• Solid understanding of multi-scenario STA and timing constraints
• Hands on experience in timing/SDC constraints generation and management
• Familiarity with synthesis and DFT related flows
• Deep understanding of designs' constraints development
• Excellent understanding of margining methodologies (OCV/AOCV/POCV)
• Timing margins fundamental from synthesis to signoff