System Verification Engineer

As an FPGA Verification Engineer, you will play a pivotal role in ensuring the quality and reliability of our complex FPGA designs. You will be responsible for developing, implementing, and executing comprehensive verification plans that span from block-level to full-chip verification. Working closely with FPGA designers and software developers, you will utilize your expertise in System Verilog UVM and CDV methodologies to architect, code, and analyze verification environments, ensuring that our products meet the highest standards of performance and functionality.

Responsibilities:

• Design and develop verification environments for FPGA components in complex projects
• Architect, code, and implement verification plans, including coverage planning, test case generation, and execution
• Conduct thorough verification activities to identify and resolve design issues
• Analyze verification results and provide feedback to design teams
• Collaborate closely with FPGA designers and software developers to ensure seamless integration and verification
• Stay up-to-date with the latest verification methodologies and tools

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Software Engineering.
• A Master's degree is a plus.
• Significant experience in object-oriented programming (OOP).
• 5+ years of experience in developing and verifying FPGA designs using System Verilog UVM or Specman
• Familiarity with VHDL and Verilog
• Experience working in a LINUX environment
• Experience writing scripts is a plus
• Experience with regression management tools is a plus