Formal Verification Engineer

R&DFormal Verification EngineerPetah TikvaFull timeThe Radar VLSI team at Mobileye EyeC is looking for an experienced Formal Verification Engineer to join us! This is a newly established team with a mission to integrate Formal Verification as a key methodology in Radar projects. Be part of a cutting-edge group designing chips for radar systems in ADAS and autonomous vehicles, where your expertise will have a significant impact.What will your job look like:You will verify unique and complex design blocks.Help determine the Formal strategy and methodology for the team.Explore new Formal methods and tools.All you need is:4+ years of experience in Formal Verification.Strong debug skills.In-depth knowledge of how Formal works.Experience in System Verilog - Advantage.Knowledge in Industry Standard protocols such as AXI/OCP/APB - Advantage.Experience with multiple clock domains during cover block by Formal.Knowledge of the following programming languages: Perl/Bash/Tcl/Python.Experience with Hardware Verification concepts and tools (UVM).