Digital Verification Engineer

Join the cutting-edge team at Samsung R&D Center as we embark on shaping the future of technology today. Beyond merely envisioning the horizon, we are actively pushing boundaries in various key areas of innovation. Samsung is committed to pioneering continuous advancements, delivering value to society, and fostering an environment where our employees can fully unleash their talents, creativity, and passion. Join us in building the tomorrow we envision,

The Group

The R&D center is part of Samsung’s world-leading Flash memory division, which is responsible for developing and manufacturing SSD, eMMC/UFS, and emerging memory products.

The center conducts research and development of signal processing algorithms and system architecture for Samsung’s next generation platforms. The team includes experienced researchers in the fields of machine learning, signal processing, compression and deduplication, error correction coding and de-noising, encryption and data security, memory system architecture and management algorithms. We offer the candidates a unique opportunity for personal development.

What will you do?

Design and develop verification environment for state-of-the-art Flash solution IPs, working closely with Design and Algorithm engineers.

Leading the top-level IP verification effort from planning to delivery.

Plan the verification of complex digital design IP’s by fully understanding the design specification and the implemented algorithms.

Working closely with architecture, design and algorithm teams to identify important verification scenarios.

Responsible for the full life cycle of verification, from verification planning to tests execution through IP environment building using System Verilog and UVM.

Define and establish new verification methodologies in the group.

We offer unique opportunity to define IPs verification from early stages of architecture definition and all the way to Tapeout.

Requirements

• BSc. in Electrical Engineering/ Computer Science
• At least 5 years of hands on experience in VLSI verification
• Advanced knowledge of ASIC verification flows with System Verilog and UVM
• Experience in developing test benches from scratch
• Familiarity with scripting languages