We are looking for an ASIC Verification engineer with a good grasp of the entire verification process – plan, execution, and sign-off, excellent analytical skills, technical skills, and high motivation to join our team and take part in the success.

Join an innovative and strong ASIC team that will give you the unique opportunity to engage in the entire chip definition and development flow, combining digital and analog circuit designs, from system and architecture to ramp to production.

What you will be doing:

• Create a thorough verification plan out of IP specification and implement it to completeness.
• Build UVM-compliant IP verification environment from scratch.
• Debug to find the root cause of issues.
• Full-chip verification from planning stage to tape-out, including gate-level testing.
• Testing using SystemVerilog and C.
• Work in a diverse environment, collaborating with power engineers, communication experts, and SW developers.

Requirements:

• B.Sc. in Electrical Engineering from a leading university.
• 3-5 years of experience in ASIC Verification roles
• Experience working with SystemVerilog- must.
• Experience working with UVM - advantage
• Experience in building IP verification environment- advantage
• Experience in embedded C programming – advantage.