Senior Formal Verification Engineer

•; Ramp up Formal Verification domain in our group, and shape the Formal strategy
• Build from scratch and fully own the end-to-end formal verification lifecycle, from verification planning, methodology definition to execution and deployment of new formal flows.
• Design, build, and maintain formal verification methodology for complex and innovative hardware designs.
• Drive the definition and implementation of scalable formal flows that grow with increasing design and project complexity.
• Collaborate closely with Architecture and Design teams to ensure correct intent, robust specifications, and efficient verification strategies.
• Act as a technical leader, influencing best practices and mentoring others in formal verification methodologies.
• Evaluate & deploy formal tools, flows, and methodologies to improve formal verification convergence.
דרישות התפקיד
• BSc or MSc in Electrical Engineering or Computer Science.
• 5+ years of hands-on experience in formal verification.
• Strong knowledge of formal verification methodologies and convergence strategies
• Proficiency in Verilog/System Verilog.
• Comfortable working in Unix/Linux environments.
• Proven experience developing formal verification environments from scratch.
• Excellent communication, analytical, debugging and problem-solving skills.
• A creative mindset—able to think outside the box and find elegant solutions to complex verification challenges.
• Scripting skills in Python.
Advantages
• Experience in the AI hardware acceleration domain.
• Solid experience with Jasper formal verification tools.