senior sta engineer, sub-chip

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
perform advanced static timing analysis (sta) for hsio at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.
ai use for timing optimization and  data analysis.

דרישות:

b.sc./ m.sc. in electrical engineering.
at least 5+ years of hands-on sta experience.
experience in prime time and signoff methodologies.
a great teammate who thrives in a collaborative environment.
ai tools orientation or alternatively a desire to learn.
ways to stand out from the crowd:
agentic frameworks.
ai prompting experience.
experience in  Linux environments.
tcl,  Python, shell scripting abilities.
experience with  data collection and analysis. המשרה מיועדת לנשים ולגברים כאחד.