senior design engineer, google cloud networking

we're the driving team behind groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking,  data center operations, systems research, and much more.
responsibilities
define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
perform rtl development (e.g., coding and debug in verilog, systemverilog, vhsic hardware description language (vhdl)), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power, and fpga/silicon bring-up.
participate in  TEST plan and coverage analysis of the block and  SOC -level ver

דרישות:

minimum qualifications:
bachelor's degree in electrical engineering, computer engineering,  Computer Science, or a related field, or equivalent practical experience.
8 years of experience architecting networking asics from specification to production or equivalent experience.
experience developing rtl for asic subsystems.
experience in micro-architecture, design, verification, logic synthesis, and timing closure.
preferred qualifications:
experience working with design networking: remote direct memory access (rdma) or packet processing and  system design principles for low latency, high throughput, security, and reliability.
experience architecting networking switches, end points, and hardware offloads.
experience working with software teams optimizing the hardware/software interface.
experience in a procedural programming language (e.g.,  C ++,  Python, go).
knowledge of tcp, ip, ethernet, pcie and dram.
familiarity with network on chip (  NOC ) principles and protocols (ax