DevOps Engineer for ASIC/FPGA Design Verification (1282)

This position works closely with hardware design and verification engineers to align DevOps solutions with the semiconductor development lifecycle. While you don’t need to have been a design or verification engineer yourself, experience in chip development workflows is required to understand our environment. If you’re passionate about automation in the context of chip design, familiar with verification tools (such as SystemVerilog UVM, Specman for e language, Cadence Xcelium simulator), and excited to collaborate with cutting-edge hardware teams, we welcome you to join RAD’s innovative verification group.

Location:

This is a full-time position based in Be'er Sheva with the option of working from home work 1 day per week.

Responsibilities:

Jenkins CI Management: Install, configure, and maintain Jenkins servers and regression job pipelines for ASIC/FPGA verification. Ensure high availability and optimal performance of the CI environment to handle compute-intensive simulation regressions.

Pipeline & Automation Development: Create and optimize CI/CD pipelines (using Jenkins Groovy scripts) and automation scripts (Python, Bash, csh) to streamline chip verification workflows – for example, automating design builds, running simulations, collecting coverage, and managing test results.

Cadence vManager Integration: Plan and execute the integration of Cadence vManager (verification management and reporting tool) with Jenkins for enhanced regression tracking, coverage analysis, and result reporting in our verification environment.

Linux Systems Administration: Oversee Linux server installation, configuration, and maintenance for verification compute servers. Manage user accounts, credentials, and permissions, ensuring secure and organized access for design and verification engineers using the infrastructure.

Server Monitoring: Continuously monitor Linux servers and EDA tool farms to ensure optimal performance. Proactively identify and resolve issues before they impact verification tasks or project schedules.

Reporting & Dashboarding: Automate and maintain verification dashboards and reports that clearly summarize regression results, test outcomes, and coverage metrics. Ensure verification teams have up-to-date visibility into progress and quality metrics.

Collaboration: Work closely with ASIC/FPGA verification engineers and hardware design teams to support their use of CI tools and environments. Troubleshoot environment issues affecting simulations or regressions, gather feedback, and continuously improve verification processes to align with hardware development needs.

Requirements:

Experience: 3+ years in DevOps, CI/CD, or Linux systems engineering roles supporting development teams. Experience in a semiconductor/chip development environment (hardware or software verification, EDA tooling support, etc.) is required.

Domain Knowledge : Familiarity with the chip design and verification cycle. While being an ASIC/FPGA design or verification engineer is not mandatory, you must have hands-on exposure to related workflows – for example, board design/bring-up, digital synthesis, static timing analysis, place-and-route, firmware/software development for chips, or QA testing in silicon projects.

Linux Proficiency: Extensive hands-on experience with Linux server administration – installations, network and security configuration, software/toolchain setup, and troubleshooting. Comfortable managing user accounts, SSH access, and performance tuning on Linux systems.

Jenkins Expertise: Proven experience installing and managing Jenkins CI environments, including creating pipelines (Groovy DSL), managing plugins and build nodes, and optimizing Jenkins for large-scale or heavy workloads (such as extensive simulation regressions).

Scripting Skills: Proficiency in scripting and automation (Python, Bash, Groovy, csh). Ability to write and maintain scripts to manage verification jobs, tool environment setups, data processing, and other automation tasks in the chip verification flow.

CI/CD Knowledge: Familiarity with CI/CD best practices and methodologies. Experience integrating various tools (compilers, simulators, linters, etc.) into automated workflows to improve efficiency and reliability of verification cycles.

Communication: Effective communication and documentation skills. Able to collaborate in a multidisciplinary technical team, gather requirements from engineers, and clearly document CI processes and user guides.

Education: B.Sc. in Computer Science, Computer Engineering, Electrical Engineering or a related field; or equivalent hands-on experience in relevant domains.

Nice to Have (Preferred Qualifications)

ASIC/FPGA Verification Background (Strongly Preferred): Direct experience as an ASIC or FPGA design verification engineer is a major plus. Candidates who have written verification testbenches or run simulations (using SystemVerilog UVM, Specman/e, etc.) and managed coverage and debugging in a chip project will find this role highly synergistic.

Cadence Tool Suite Experience: Hands-on experience with Cadence verification tools like vManager and Xcelium (or similar simulators), especially in integrating these tools into CI pipelines or using them in large-scale regression environments.

Distributed Computing: Experience managing compute farms or job schedulers (e.g., LSF, PBS) to distribute EDA workloads efficiently. Understanding how to scale verification regressions across multiple machines or cores.

Infrastructure as Code & Scripting: Familiarity with infrastructure-as-code tools (Docker, Kubernetes, Terraform, etc.) or additional scripting languages. A willingness to learn new technologies and apply them to improve our hardware verification infrastructure.

DevOps in Hardware Environments: Previous experience in a semiconductor or FPGA development organization, with understanding of the unique challenges of CI/CD for hardware (e.g., licensing for EDA tools, long-running simulation jobs, hardware-in-loop testing).