STA engineer

We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams.DescriptionYou will be responsible for:Develop/support automated block and full chip level signoff flowsFull Chip Timing/Noise convergence and full signoff for high quality TOEnable hierarchical Timing flowsPower optimizationsGenerate block level budget and context for correlation with Full ChipDrive custom IP integration and custom timing checks flowsClose work with Design, DFT, architecture and Power teamPreferred QualificationsAdvantage - Understanding noise and signal integrity effectsAdvantage - Timing margins fundamental from synthesis to signoffAdvantage - Experience with scriptingMinimum Qualifications4+ years experience in Static Timing analysisExtensive experience with one of the commercial STA toolsFamiliarity with hierarchical design approach, top-down design, timing and physical convergenceExperience with backend STA closure and SignoffDeep understanding of designs' constraints developmentGood understanding of AC timing from specs to implementationGood understanding of DFT modes and their constraintsGood communication skills and team playerQuick learning of flows and methods","internalDetails":null,"eeoContent":null