DFT Engineer for AMS Group

SummaryPosted: Apr 30, 2024Role Number:200548905Will you help us design future generations of revolutionary Apple products? Are you an engineer with a strong foundation and real passion for building new technologies? Do you have track record leading DFT efforts for complex chip designs? Imagine what you could do here. At Apple, new ideas have a way of becoming excellent products, services, and customer experiences very quickly. Every single day, people do amazing things at Apple. Do you want to impact billions of users by developing extraordinary products with a prime focus on accuracy and performance of the product? So Join us! We want you to join our team if you are an innovative engineer with the dream to research and develop solutions that do not yet exist. In this highly visible role, you will be at the centre of a System-on-Chip design effort. collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly.DescriptionLead the complete DFT solutions in a chip design by working with chip DFT team to document DFT specifications, and define the SoC test interface develop and implement DFT architecture work with the validation team to verify DFT implementations and implement design changes generate structural test vectors, analyze and improve coverage work with designers on STA, physical, power and logical issues work with Test Engineers to bring up test vectors on silicon.Minimum QualificationsMinimum QualificationsKey Qualifications5+ years of DFT experience, leading DFT efforts for complex chip designsExpertise and knowledge about industrial standards and practices in DFT - including ATPG, JTAG, MBIST and trade-offs between test quality and test timeExperience developing DFT specifications and driving DFT architecture and methods for designsExperience with Verilog and / or VHDL, and with simulators and waveform debugging toolsDemonstrating proven understanding of design verification (DV) methodologies for validating DFT implementation in simulation pre-siliconDebug ATPG patterns, compressed ATPG patterns, MBIST, and JTAG/1500 related issuesExperienced with STA constraints development and analysis for DFT modes and SDF simulationsPreferred QualificationsPreferred QualificationsEducation & ExperienceBSc or MSc in Electrical Engineering or Computer EngineeringAdditional RequirementsMore