VLSI DFT engineer- Graduate position

Ramat-Gan (Tel-Aviv area)
About The Position

We are looking for a talented Graduate DFT engineer

As a DFT Engineer (Graduate) you will work closely with all other design teams – backend, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT) methodologies for highly complex digital and mixed-signal chips. You will work on silicon test strategies, DFT/DFD, BIST for complex next generation SoCs.

Requirements

Minimum qualifications:

Master's degree in electrical engineering from a well-known university.
Average grade above 85

Preferred qualifications:

Work experience in vlsi
Familiarity with EDA tools, dft concepts
Understanding of VLSI ASIC development flow
Excellent attention to detail, along with strong organizational, problem-solving, and communication skills.

Responsibilities:

Participate in implementing SoC DFT (ATPG/DFT/MBIST).
Work on hierarchical design and SSN technology.
Debug Design Rule Checks (DRC) and apply design fixes to achieve high test quality.
Insert DFT logic, including boundary scan, scan chains, DFT Compression, Logic BIST, TAP controllers, Clock Control blocks, and other DFT IP blocks.
Insert and integrate MBIST logic.
Run GTL and RTL simulations.
Work on and implement test plans for special analog IPs.
Support DFT ramp-up, test program integration, and pattern deployment in tester/ATE environments.
Generate, verify, and optimize ATPG patterns (stuck-at, at-speed, and transition faults) to maximize test coverage.
Document DFT working processes.