Cellular L2-3 Architecture & System Engineer

At Apple, we’re developing groundbreaking cellular chipsets that power the next generation of wireless technologies-from advanced 5G to future 6G systems. We’re looking for a highly motivated and top-ranked Cellular L2-3 Architecture & System Engineer to join our world-class team. This role sits at the intersection of hardware and software and plays a critical part in defining the cellular data plane architecture (layers 2 and 3)-spanning the full stack from the Application Processor interface to the physical layer. While prior cellular or wireless experience is an advantage, it is not a strict requirement. We welcome candidates with strong hardware systems experience, a proven ability to learn quickly, and the confidence to operate in multidisciplinary and cross-functional environments.

Description

The Cellular Data Plane includes all L2 and L3 layers in the user equipment (UE): from the Application Processor (AP) interface to the PHY interface in the uplink, and from the PHY interface to the AP in the downlink. This encompasses the 5G/4G L2 protocol layers-SDAP, PDCP, RLC, MAC-and also higher-layer classification and processing functions tied to L3, related to the end-to-end network stack (e.g., IP, QoS, etc.). As a L2-3 System Engineer, you’ll be a key driver of end-to-end system definition, owning data flow definition, HW/SW partitioning, hardware interface design, and trade-offs around area, power, and performance. You’ll collaborate across multiple disciplines-including protocol design, modem SW, HW, SoC implementation-while influencing decisions that shape Apple’s future cellular architecture. The role also involves contributing to hardware definition and modeling, participating in early silicon validation, and de-risking the system through architectural clarity and rigorous technical analysis. Our team holds a pivotal position in Apple’s cellular organization - enabling innovation, ensuring integration, and delivering efficient, scalable solutions.

Minimum Qualifications

Minimum of 8 years of experience in hardware architecture, hardware design, or system engineering in data plane systems (including but not limited to L2/L3, MAC, protocol processing, or networking subsystems).
Proven hardware-centric mindset with strong attention to detail.
Solid technical breadth across HW/SW interfaces, protocol layering, and performance trade-offs.
Hands-on experience in system-level analysis, modeling, and optimization.
Capable of writing, reviewing, and owning engineering requirement specifications.
Experience in system integration and cross-functional collaboration.
Strong teamwork and communication skills, both written and verbal.
Fluent in English, with the ability to lead technical reviews and author high-quality documents.
BS or MS in Electrical Engineering, Computer Engineering, or a related field.

Preferred Qualifications

Familiarity with cellular data plane protocols (4G/5G), including SDAP, PDCP, and QoS handling.
Experience with SoC architecture and validation for data plane or communications systems.
Understanding of IP networking and protocol stacks, including packet flow classification and QoS enforcement.
Working knowledge of the PHY layer to ensure coh
erent L2-PHY integration and interface definition.
Experience with Python and/or C/C++ for modeling, simulation, or algorithm development.
Prior involvement in lab testing, silicon bring-up, and use of hardware validation tools and equipment.
Advanced degree (MS or PhD) in Electrical or Computer Engineering.

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