Design Verification Team Leader, Nitro Team

DESCRIPTION

Annapurna Labs is the team behind AWS Nitro, the purpose-built system that powers the security, performance, and innovation of every EC2 instance. We operate like a start-up with the scale of the world's largest cloud provider.

We're looking for a Design Verification Team Lead - a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Nitro system SoC, the foundation of AWS's virtualization, networking, and storage offload infrastructure.

It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written

It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack, with particular emphasis on networking workloads such as ENA and EFA

It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality

It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development

Key job responsibilities

- Develop and execute verification plans for IO sub-systems - covering interconnect protocols, peripheral interfaces, and system-level integration with a strong connection to networking flows (ENA/EFA)

Verify IO sub-system features, including interconnect protocols and various accelerator engines

Develop and debug C embedded SW as part of hardware-software integration verification

Build and maintain UVM-based verification environments for various clusters and sub-systems

Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance

Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability)

Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions

Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable

- Contribute to performance verification - ensuring micro-architectural implementations meet performance targets alongside correctness

A day in the life

As a Design Verification Team Lead on the Nitro team, you will be responsible for leading the verification of complex SoC sub-systems, driving industry-leading verification methodologies, and ensuring our next-generation Nitro system SoC meets the highest quality bar before reaching silicon.

About the team

What Sets Us Apart?

Full system ownership - our verification leaders gain deep understanding of all system flows and the full SW stack, truly owning the technical scope from product definition through post-tapeout activities. This end-to-end ownership is what defines verification at Annapurna Labs

Agentic AI is embedded in our workflow - not as an experiment, but as a core part of how we design and verify chips

Cutting edge methodologies drive every stage of our verification process

Relentless innovation - we don't settle; we actively seek new approaches that raise the bar on silicon quality

We do classic functional verification (SV/UVM/TLM), but beyond that, we touch physical design aspects, to ensure that the quality of our silicon is beyond logical functionality

Performance optimization at all levels is at the heart of our targets on top of logical correctness verification

Our verification underpins the infrastructure that runs millions of active workloads across AWS, where networking performance and security are non-negotiable

BASIC QUALIFICATIONS

8+ years of experience in design verification of complex SoC or ASIC projects
Strong communication skills with the ability to collaborate across design, software, and physical design teams
Proven track record leading verification of IO sub-systems, interconnect fabrics, or system-level integration blocks
Deep expertise in UVM/SystemVerilog-based verification environments
Experience driving verification from product definition through post-tapeout silicon validation
Experience with performance verification methodologies alongside functional correctness

PREFERRED QUALIFICATIONS

Strong knowledge of ARM interconnect protocols (AMBA CHI/ACE/AXI) and coherency verification
Experience with IO virtualization verification (SMMU, TLB, page table walks, memory attributes)
C/C++ embedded software programming and firmware-level debug skills
Experience with hardware-software co-verification
Familiarity with networking data paths and offload architectures
Understanding of physical design aspects and their impact on functional verification (e.g., clock domain crossings, power-aware verification)

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